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Parasitic elements play a major role in advanced circuit design and pose considerable run-time and memory problems for the post-layout verification, especially in the case of full-chip extraction. This brief presents a realizable R(L)C(M)-netlist-in-R(L)C(M)-netlist-out method to sparsify and reduce the capacitive coupling parasitics in circuits with interconnect lines. The method is applicable in conjunction with partitioning-based model-order reduction algorithms to reduce the complete extracted netlists, or as a stand-alone tool to process only the capacitive coupling. It is shown that, by using the method, circuits with even dense capacitive coupling can be partitioned and reduced efficiently.
Very Large Scale Integration (VLSI) Systems, IEEE Transactions on (Volume:PP , Issue: 99 )