Skip to Main Content
In this paper, a new technique for the implementation of MIL-STD-1553B bus protocol on FPGA board using digital phase lock loop is presented. Digital phase lock loop (DPLL) is used for data clock recovery from encoded manchester data of the channel at receiver end, instead of implementing common practice of initiating a separate clock for encoded manchester data processing. Usage of DPLL, resolves the synchronization issues, a major concern in high data rate embedded systems and increases the integrity and reliability of the system. Proof of concept is validated by implementing a 1553B bus transaction (BC to RT) on FPGA board with its different modules like UART, Bus controller, Manchester encoder/decoder and Digital phase lock loop.