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Micro-architecture of the VAX 9000

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4 Author(s)

The VAX 9000 CPU, a high-performance scalar processor with an integrated vector facility, is discussed. The implementation of the macropipeline found in the four major subsystems of the VAX 9000 is highlighted. The subsystems are the instruction fetch and decode unit (IBOX), the execution unit (EBOX), the data cache and main memory interface (MBOX), and the vector processing unit (VBOX). IBOX combines a 1-cycle access virtual instruction cache with a 25-B instruction buffer and an instruction decode crossbar. The VAX 9000 EBOX performs all scalar operations. It is a pipelined design incorporating a microsequencer to control functional unit operation. The MBOX of the VAX 9000 is the primary source of memory data, and so it is the home of the actual address translation buffer and the data cache. It is multiported and pipelined with two autonomous pipeline segments. The VBOX is an optional arithmetic unit which accelerates arithmetic-intensive code applications.<>

Published in:

Compcon Spring '90. Intellectual Leverage. Digest of Papers. Thirty-Fifth IEEE Computer Society International Conference.

Date of Conference:

Feb. 26 1990-March 2 1990