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Device mismatch has long prevented the implementation of accurate high density analog computation. This paper presents the Reconfigurable Analog Signal Processor (RASP) 2.9a, a 350 nm double-poly CMOS chip designed for the implementation of accurate analog computation. The chip is the densest field programmable analog array (FPAA) to date, containing over 130 k programmable floating gate switch elements (SWEs). The paper reviews an algorithm for rapidly programming the charge on floating gate switch elements with 10.2 bit accuracy. An automated algorithm based on the EKV transistor model is developed to rapidly characterize device mismatch, the Early effect, capacitive drain coupling, and temperature dependent behavior. This paper empirically verifies the characterization, using the precise floating gate programming methods to offset the errors and create current sources with 2.2% RMS error over a dynamic range of 25 dB. The current sources are then modified to create current mirrors and vector-matrix multipliers, accurate for currents down to 8 nA. Together with the computational analog blocks, these linear circuits can be synthesized into a wide range of extremely low power linear and nonlinear functions. The calibration routine, in combination with preexisting design tools, allows the automated synthesis, placement, and accurate programming of large classes of circuits on an FPAA.
Circuits and Systems I: Regular Papers, IEEE Transactions on (Volume:60 , Issue: 3 )
Date of Publication: March 2013