Skip to Main Content
This paper presents the characterization and design of a static random access memory (SRAM) cell at nanoscale ranges. The proposed SRAM cell incorporates a single-electron (SE) turnstile and an SE transistor/MOS circuit in its operation, hence the hybrid nature. Differently from previous cells, the hybrid circuit is utilized to sense (measure) on a voltage basis the presence of at least an electron as stored in memory, while the turnstile enables the SE transfer in and out of the storage node. The two memory operations (read and write) are facilitated by utilizing these hybrid circuits; moreover, the proposed SRAM cell shows compatibility with MOSFET technology. HSPICE simulation shows that the proposed SRAM cell operates correctly at 45 and 32 nm with good performance in terms of propagation delay, signal integrity, area, stability, and power consumption. The extension of the aforementioned hybrid design to a ternary content addressable memory cell is also presented.