In Situ Profile Control with Titan Edge?? Heads for Dielectric Planarization of Advanced CMOS Devices

The performance and yield of advanced CMOS devices directly depend on the control of film thickness variation during every Chemical Mechanical Polishing (CMP) step, as multiple CMP steps are required to define the structures for the integration schemes for high-k metal gate (HKMG). As a consequence, CMP requirements are becoming increasingly stringent. This paper highlights new process control technologies which enable efficient and cost-effective solutions for dielectric and poly CMP steps, including FullVision(r) endpoint & In Situ Profile Control (ISPC(TM)) using next generation Titan Edge(TM) polishing heads. The ISPC system controls both wafer-to-wafer and within-wafer post-polish thickness non-uniformity for dielectric and poly CMP. The ISPC system is an alternative to runto- run methods for controlling polishing profiles, making real-time profile adjustments for either stop-in-film or stop-on-film applications. This paper presents results for stop-in-oxide polishing with ceria slurry for Inter layer dielectric - level 0 (ILD0) and Shallow Trench Isolation (STI) test patterned films. Keywords: Planarization, Chemical Mechanical Polishing, In Situ Profile Control, ISPC, FullVision Endpoint, High-k Metal Gate, Multi-zone Polishing Head, Advanced Process Control