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In this paper, the authors build a new modelling framework for the timing behaviour of a flipflop by putting the clock-to-q delay into a nonlinear functional relationship with the data/clock alignment of the flipflop. This new framework opens new perspectives into the functioning of a digital circuit by viewing it as a fully interconnected and interdependent system. Consequently, the traditional method for timing analysis is rendered insufficient. An iterative timing analysis method is then developed to solve two related problems. One is to check whether a circuit can work at a given clock period; the other is to determine the minimal clock period of a circuit. Experimental results show that a reduction of the clock period is achieved and its significance is observed especially when process variation is considered.