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Design and management of high-performance, reliable and thermal-aware 3D networks-on-chip

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6 Author(s)
A. -M. Rahmani ; Turku Centre for Computer Science (TUCS), 20520 Turku, Finland ; K. R. Vaddina ; K. Latif ; P. Liljeberg
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Increasing the number of cores over a 2D plane is not efficient in hyper-core systems due to long interconnects. As a viable alternative over the 2D planar chip, 3D integrated technology offers greater device integration and shorter interlayer interconnects. 3D networks-on-chip (NoC)-bus hybrid mesh architecture, which is a hybrid between packet-switched network and a bus, was proposed to take advantage of the intrinsic attributes of 3D ICs. Even though this architecture was proposed as a feasible one to provide both performance and area benefits, the challenges of combining both media (NoC and bus) to design 3D NoCs have not been addressed. In this study, an efficient 3D NoC architecture is proposed to optimise performance, power consumption and reliability of 3D NoC-bus hybrid mesh system. The mechanism benefits from a congestion-aware and bus failure tolerant routing algorithm called `AdaptiveZ' for vertical communication. In addition, the authors propose thermal-aware scheduling strategy in order to mitigate temperature by herding most of the switching activity closer to the heatsink. To estimate the efficiency of the proposed architecture, the system has been simulated using uniform, hotspot 10% and negative exponential distribution traffic patterns. In addition, a videoconference encoder has been used as a real application for system analysis. Compared with a typical stacked mesh 3D NoC, our extensive simulations demonstrate significant power, performance and peak temperature improvements.

Published in:

IET Circuits, Devices & Systems  (Volume:6 ,  Issue: 5 )