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In this study, the authors present an accurate approach for the estimation of statistical distribution of leakage power consumption in the presence of process variations in nano-scale complementary metal oxide semiconductor (CMOS) technologies. The technique, which is additive with respect to the individual gate leakage values, employs a generalised extreme value (GEV) distribution. Compared with the previous methods based on (two-parameter) lognormal distribution, this method uses the GEV distribution with three parameters to increase the accuracy. Using the suggested distribution, the leakage yield of the circuits may be modelled. The accuracy of the approach is studied by comparing its results with those of a previous technique and HSPICE-based Monte Carlo simulations on ISCAS85 benchmark circuits for 45 nm CMOS technology. The comparison reveals a higher accuracy for the proposed approach. The proposed distribution does not add to the complexity and cost of simulations compared with the case of the lognormal distribution based on the additive approach.