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Code optimization as a side effect of instruction scheduling

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1 Author(s)
Gupta, R. ; Dept. of Comput. Sci., Pittsburgh Univ., PA, USA

An instruction scheduler utilizes code reordering techniques for generating schedules in which instructions can be issued without delays. In order to perform code reordering across branches, code motion is performed that hoists some instructions above branches and sinks others below branches. Following code reordering, compensation code must be introduced in order to preserve program semantics. In this paper, we demonstrate that several important code optimizations can be performed as a side-effect of generating compensation code. These optimizations include partial redundancy elimination, partial dead code elimination, elimination of redundant loads and elimination of dead stores. We demonstrate how existing data-flow frameworks for these optimizations can be extended for generating optimized compensation code

Published in:

High-Performance Computing, 1997. Proceedings. Fourth International Conference on

Date of Conference:

18-21 Dec 1997