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A Reconfigurable and Power-Scalable 10–12 Bit 0.4–44 MS/s Pipelined ADC With 0.35–0.5 pJ/Step in 1.2 V 90 nm Digital CMOS

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2 Author(s)
Taherzadeh-Sani, M. ; Dept. of Electr. & Comput. Eng., McGill Univ., Montreal, QC, Canada ; Hamoui, A.A.

A pipelined ADC, reconfigurable over bandwidths of 0.2-22 MHz (sampling frequencies of 0.4-44 MS/s) and resolutions of 10-12 bits, is described for applications in multi-standard wireless terminals. Fabricated in a 1.2-V 90-nm digital CMOS technology, this ADC achieves low power (figure-of-merit of FOM=0.35 to 0.5 pJ per A/D conversion step) over its full bandwidth-resolution range. Accordingly, compared to state-of-the-art power-efficient reconfigurable pipelined ADCs, this ADC provides a larger bandwidth-resolution reconfigurability space, while maintaining a highly competitive FOM over this entire space. To achieve such low-power performance in a low-voltage nanometer CMOS process, this work utilizes: (1) a current-scalable frequency-compensation technique to design low-power current-scalable two-stage opamps; (2) a switched-capacitor technique to design dynamic comparators with low input capacitance (input-loading effect); and (3) a low-power digital background gain-calibration technique. The large bandwidth and resolution reconfigurability ranges are achieved using current-scaling and stage-bypass techniques, respectively.

Published in:

Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 1 )

Date of Publication:

Jan. 2013

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