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A 16-mW 78-dB SNDR 10-MHz BW CT \Delta \Sigma ADC Using Residue-Cancelling VCO-Based Quantizer

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7 Author(s)
Reddy, K. ; Sch. of Electr. Eng. & Comput. Sci., Oregon State Univ., Corvallis, OR, USA ; Rao, S. ; Inti, R. ; Young, B.
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This paper presents a continuous-time (CT) ΔΣ modulator using a VCO-based internal quantizer. It incorporates a nonlinear VCO as the second stage in a two-stage residue canceling quantizer (RCQ) and mitigates the impact of its nonlinearity by spanning only a small region of the VCO's V-to-F nonlinear tuning curve. The order of noise shaping is increased by placing the RCQ in a continuous-time ΔΣ loop. Using only a first order loop filter, the proposed ΔΣ modulator achieves second order noise shaping. Fabricated in a 90-nm CMOS process, the prototype modulator occupies an active area of 0.36 mm2 and consumes 16 mW power. It achieves a peak SNDR of 78.3 dB in 10-MHz bandwidth and an SFDR of better than 85 dB when clocked at 600 MHz. The figure of merit of the modulator is 120 fJ/conv-step.

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:47 ,  Issue: 12 )

Date of Publication:

Dec. 2012

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