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A 14.2 mW 2.55-to-3 GHz Cascaded PLL With Reference Injection and 800 MHz Delta-Sigma Modulator in 0.13 \mu m CMOS

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2 Author(s)
Dongmin Park ; Qualcomm Inc, San Diego, CA, USA ; SeongHwan Cho

In this paper, a low-noise cascaded PLL is proposed where an integer-N digital bang-bang PLL is used to multiply a 50 MHz reference to an 800 MHz clock that is fed to a ΔΣ fractional-N PLL to generate 2.55-to-3 GHz output. In order to minimize the jitter of the 800 MHz clock, a reference injection scheme using dual-pulse ring oscillator is employed. Quantization noise from the delta-sigma modulator is suppressed without any noise cancellation techniques owing to the high operating frequency of the fractional-N PLL. Prototype implemented in 0.13 μm CMOS process achieves the worst-case RMS jitter of 356 fsrms over 100 Hz to 40 MHz integration bandwidth, while consuming 14.2 mW from a 1.2 V supply. The worst-case fractional spur measured over 7 different chips is -53.9 dBc and the reference spur is -84 dBc.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 12 )