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This paper presents an asynchronous pipelined all-digital 10-b time-to-digital converter (TDC) with fine resolution, good linearity, and high throughput. Using a 1.5-b/stage pipeline architecture, an on-chip digital background calibration is implemented to correct residue subtraction error in the seven MSB stages. An asynchronous clocking scheme realizes pipeline operation for higher throughput. The TDC was implemented in standard 0.13-μm CMOS technology and has a maximum throughput of 300 MS/s and a resolution of 1.76 ps with a total conversion range of 1.8 ns. The measured DNL and INL were 0.6 LSB and 1.9 LSB, respectively.
Date of Publication: Feb. 2013