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A 28.3 mW PA-Closed Loop for Linearity and Efficiency Improvement Integrated in a + 27.1 dBm WCDMA CMOS Power Amplifier

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5 Author(s)
Shouhei Kousai ; Center for Semicond. R&D, Toshiba Corp., Kawasaki, Japan ; Kohei Onizuka ; Takashi Yamaguchi ; Yasuhiko Kuriyama
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A wideband feedback linearization technique for a power amplifier (PA), PA-closed loop, is presented. In order to achieve wideband operation, it employs a two-path feedback scheme where the input and output phases and amplitudes are detected at RF and compared to directly control and linearize the PA. The wideband characteristic of the loop suppressed the adjacent channel leakage ratio (ACLR) for WCDMA standard by 6 dB. The advantage of the feedback is demonstrated by measuring the performance against the load variation. The required back-off is degraded by only 1 dB with a voltage standing wave ratio (VSWR) of 1.5, whereas it is 3 dB without the loop. The loop consumes 28.3 mW and it reduces the quiescent power consumption of the PA by 78 mW. The chip, which integrates the loop and PA, is fabricated in a 0.13 μm CMOS technology and the loop occupies 0.3 mm by 0.7 mm. The PA delivers WCDMA output power of 27.1 dBm with a power added efficiency (PAE) of 28% and ACLR of 40 dBc. This topology makes possible the wideband feedback linearization of a watt-level PA.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 12 )