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A new path to frame low power, high-density and fast integrated circuits has been rolled out by the observation of current-induced domain wall (DW) motion in magnetic track. As an advanced extension of this mechanism, high performance racetrack memory can be built up combining with magnetic tunnel junction (MTJ) read and write heads. The rapid progress of CoFeB/MgO perpendicular magnetic anisotropy (PMA) shows that the PMA MTJ can be scaled down to 20 nm while keeping fast data access. These recent discoveries allow us to design an ultra-high density content addressable memory (CAM), one of the most important applications of MRAM. The mainstream CAMs suffer from high power and large area as its conventional structure is composed of numerous large-capacity SRAM blocks in order to provide fast data access. MRAM based non-volatile CAMs have been proposed to relive the power consumption, however the density issue cannot be surmounted due to the large switching currents. In this paper, we present a design of NOR-type CAM based on DW motion in PMA magnetic tracks. The CMOS switching and sensing circuits are globally shared to optimize the cell area down to 6 F2/bit; the complementary dual track allows the local sensing and faster data search speed while keeping low power. By using an accuracy spice model of PMA racetrack memory and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its functionality and evaluate its high performance.