Skip to Main Content
We report our progress on material improvement, device design, wafer processing, integration with CMOS, and testing of STT-RAM memory chips at 54 nm node with cell sizes of 14 and 28 F2 (F=54 nm). A dual tunnel barrier MTJ structure was found to have lower and more symmetric median spin transfer torque writing switching currents, and much tighter parallel to antiparallel switching current distribution. In-plane MTJ devices write endurance data, read and write soft error rates data and simulation fits, and solutions to the long write error rate tail at fast write speeds are discussed.
Date of Publication: Nov. 2012