A 190- zero-IF GFSK Demodulator With a 4-b Phase-Domain ADC

This paper presents a zero-IF Gaussian frequency-shift keying (GFSK) demodulator based on a phase-domain analog-to-digital converter (Ph-ADC) which directly quantizes the phase information of the received complex baseband signal. The Ph-ADC linearly combines the in-phase and quadrature parts of the incoming signal, and the generated phase-shifted versions are fed to comparators to detect the zero-crossings and build a 4-b digital representation of the signal phase. Seeking for a low-area and low-power consumption realization, our proposal employs a resistor-less scheme which performs phase rotations in current domain. Together with the Ph-ADC, the fully integrated GFSK demodulator also includes a channel-filtering programmable gain amplifier and a symbol decision block. Altogether, the demodulator occupies 0.14 mm² in a 0.13- μm CMOS technology with a total power consumption of 190 μW from a 1-V supply. For a data rate of 1 Mbps and 0.5 modulation depth, the GFSK demodulator requires an E_B/N₀ of 14.8 dB for a bit error rate of 0.1% considering a flicker noise corner of 150 kHz, obtains a dynamic range of 74 dB, and is able to tolerate carrier frequency offsets of ±170 kHz. This performance safely complies with the requirements of the Bluetooth Low Energy (BLE) standard.