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Are QCA cryptographic circuits resistant to power analysis attack?

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5 Author(s)
Weiqiang Liu ; Inst. of Electron., Commun. & Inf. Technol., Queen''s Univ. Belfast, Belfast, UK ; Srivastava, S. ; Liang Lu ; O'Neill, M.
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Quantum-dot cellular automata (QCA) technology is expected to offer fast computation performance, high density, and low power consumption. Thus, researchers believe that QCA may be an attractive alternative to CMOS for future digital designs. Side channel attacks, such as power analysis attacks, have become a significant threat to the security of CMOS cryptographic circuits. A power analysis attack can reveal the secret key from measurements of the power consumption during the encryption and decryption process. As there is no electric current flow in QCA technology, the power consumption of QCA circuits is extremely low when compared to their CMOS counterparts. Therefore, in this paper an investigation into both the best and worst case scenarios for attackers is carried out to ascertain if QCA circuits are immune to power analysis attack. A QCA design of a submodule of the Serpent cipher is proposed. In comparison to a previous design, the proposed design is more efficient in terms of complexity, area, and latency. By using an upper bound power model, the first power analysis attack of a QCA cryptographic circuit is presented. The simulation results show that even though the power consumption is low, it can still be correlated with the correct key guess, and all possible subkeys applied to the Serpent submodule can be revealed in the best case scenario. Therefore, in theory QCA cryptographic circuits would be vulnerable to power analysis attack. However, the security of practical QCA devices can be greatly improved by applying a smoother clock. Moreover, in the worst case scenario, the design of logically reversible QCA circuits with Bennett clocking could be used as a natural countermeasure to power analysis attack. Therefore, it is believed that QCA could be a niche technology in the future for the implementation of security architectures resistant to power analysis attack.

Published in:

Nanotechnology, IEEE Transactions on  (Volume:11 ,  Issue: 6 )

Date of Publication:

Nov. 2012

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