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In this paper, we propose a statistical methodology for the design of process variation tolerant yet low-power 6T SRAM cells. In addition to process variations, Negative Bias Temperature Instability (NBTI) has been included in the design methodology such that the time dependence of the failure probability is taken into account. To increase the modeling accuracy of the statistical distributions of different SRAM reliability metrics such as static noise margin (SNM) and Read Current, a modeling scheme based on nonlinear regression is suggested. The design technique, which minimizes the failure probabilities due to the process variations, considers the widths and lengths of the six transistors of the cell as design parameters. The sizes of the transistors are selected such that the area constraint is not violated. Also, to include the static power consumption of the SRAM block in the design methodology, we introduce a method for estimating the SRAM block leakage distribution. To show the efficacy of the technique, the results of applying this methodology for a 45 nm CMOS technology are presented.