By Topic

Retention time characterization and optimization of logic-compatible embedded DRAM cells

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Anh Tuan Do ; IC Design Centre of Excellence, Nanyang Technol. Univ., Singapore, Singapore ; He Yi ; Kiat Seng Yeo ; Kim, T.T.

Logic-compatible 2T and 3T embedded DRAMs (eDRAM) have recently gained their popularity in embedded applications because of their high density and good voltage margin. The most important design requirements in eDRAM cells are cell area, data retention time and read speed. In this paper, we present an in-depth analysis on the data retention time of various logic-compatible eDRAM cells, followed by the effects of several design factors on the retention time. A systematic methodology is proposed for enhancing the retention time of the eDRAM cells. Simulation results using a standard 65nm CMOS technology show that the optimization process improves the data retention time more than 3×. Finally, the number of read operations per retention period is estimated to show the effectiveness of each eDRAM cell. Analysis demonstrates that although the 2T eDRAM cell has a shorter retention time than the conventional 3T cell, it has better effectiveness due to the faster read operation.

Published in:

Quality Electronic Design (ASQED), 2012 4th Asia Symposium on

Date of Conference:

10-11 July 2012