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A 2.4 GHz Fractional-N Frequency Synthesizer With High-OSR ΔΣ Modulator and Nested PLL

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3 Author(s)
Pyoungwon Park ; Department of Electrical Engineering and Computer Science, KAIST, Daejeon, Korea ; Dongmin Park ; SeongHwan Cho

This paper presents a nested-PLL architecture for a low-noise wide-bandwidth fractional-N frequency synthesizer. In order to reduce the quantization noise, operating frequency of ΔΣ modulator (DSM) is increased by using an intermediate output of feedback divider. A PLL which serves as an anti-alias filter is added to suppress noise aliasing caused by the divider. Prototype implemented in a 0.13 μm CMOS using ring VCOs achieves 26.3 dB of quantization noise suppression while consuming 15.2 mW and occupying 0.17 mm2.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 10 )