FPGA Implementation for Real-Time Empirical Mode Decomposition

This paper presents a novel field-programmable gate array (FPGA) based method for empirical mode decomposition (EMD) in real time. Traditionally, EMD can be easily implemented and developed using a high-level computer language in a PC or DSP chip. However, it is difficult to implement EMD in a hardware environment. This paper develops EMD for real-time applications using a hardware-based FPGA. The proposed FPGA-based method calculates the upper and lower envelopes in EMD point by point by using a circular queue to temporarily store values of maxima and minima, from which the upper and lower envelopes in the EMD can be determined continuously. Additionally, an attempt is made to increase the efficiency of the computational process by cascading several identical modules as a serial pipeline structure in order to conduct an iterative loop for calculating the intrinsic mode functions in EMD. The fast process from the serial pipeline structure results in real-time computation with a sampling rate of up to 12.5 MHz and mitigation of the end effect. The proposed method is validated by the simulation results obtained by Quartus II and verified by FPGA (Altera Stratix III EP3SL150F1152C2) realization, revealing its effectiveness in real-time applications.