Referenced Items are not available for this document.
Summary form only given. Prediction of integrated circuit manufacturing yield has become the main application of developed yield models. In this paper, a different application, which is to develop tool PID/PWP limits to achieve product defect density goal, is shown. The developed limits are dynamic as most elements, such as defect size distribution, killer pareto and kill ratio change and improve from time to time. This method can be used to monitor any product yield enhancement activity in a consistent manner
Published in:
Advanced Semiconductor Manufacturing Conference and Workshop, 1997. IEEE/SEMI
Date of Conference: 10-12 Sep 1997
- Page(s):
- 144 - 145
- Meeting Date :
- 10 Sep 1997-12 Sep 1997
- ISSN :
- 1078-8743
- Print ISBN:
- 0-7803-4050-7
- INSPEC Accession Number:
- 5780954
- Conference Location :
- Cambridge, MA
- Digital Object Identifier :
- 10.1109/ASMC.1997.630722
- Product Type:
- Conference Publications
About IEEE Xplore | Contact | Help | Terms of Use | Nondiscrimination Policy | Site Map | Privacy & Opting Out of Cookies
A not-for-profit organization, IEEE is the world's largest professional association for the advancement of technology.
© Copyright 2013 IEEE - All rights reserved. Use of this web site signifies your agreement to the terms and conditions.
