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Meshes with Reconfigurable Buses

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2 Author(s)

This paper considers a mesh with reconfigurable bus (reconfigurable mesh), that consists of a VLSI array of processors overlaid with a reconfigurable bus system. The N PEs are laid out as a square mesh in O(N) VLSI area. In addition to the 4 near neighbor mesh connections between processors, the reconfigurable bus system can be used to dynamically obtain various inter-connection patterns amongst the PEs. In fact, the reconfigurable mesh can be used as a universal chip capable of simulating any O(N) area organization without loss in time. The reconfiguration scheme also supports several parallel techniques developed on the CRCW PRAM model, leading to asymptotically superior solution times compared to those on the mesh with multiple broadcast buses, the mesh-of-trees, and the pyramid computer. These features are illustrated by presenting efficient reconfigurable mesh algorithms to solve a variety of problems involving graphs and digitized images.