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A new algorithm is presented which automatically determines the optimal clocking parameters in synchronous circuits that contain level-sensitive latches, and use arbitrarily complex clocking schemes. The borrowing of time between clock phases, enabled by level-sensitive latches, comes at the cost of additional complexity for the timing analysis algorithms. An iterative algorithm is proposed here which provides a lower bound on the shortest possible cycle time at each iteration. This algorithm has been implemented in a circuit-level timing analysis program for MOS VLSI circuits.