Automatic Determination of Optimal Clocking Parameters in Synchronous MOS VLSI Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$15 $15
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, books, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)

A new algorithm is presented which automatically determines the optimal clocking parameters in synchronous circuits that contain level-sensitive latches, and use arbitrarily complex clocking schemes. The borrowing of time between clock phases, enabled by level-sensitive latches, comes at the cost of additional complexity for the timing analysis algorithms. An iterative algorithm is proposed here which provides a lower bound on the shortest possible cycle time at each iteration. This algorithm has been implemented in a circuit-level timing analysis program for MOS VLSI circuits.