By Topic

Adaptive Stackable 3D Cache Architecture for Manycores

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Guthmuller, E. ; LETI, CEA, Grenoble, France ; Miro-Panades, I. ; Greiner, A.

With the emergence of many core architectures, the need of on-chip memories such as caches grows faster than the number of cores. Moreover the bandwidth to off-chip memories is saturating. Big memory caches can alleviate the pressure to off-chip accesses. In this paper, we present an adaptive 3Dcache architecture taking advantage of dense vertical connections in stacked chips. Then we propose a dynamically adaptive mechanism to optimize the use of the aforementioned 3D cache architecture according to the workload needs. Finally, we analyze the gain on memory accesses and on software execution time in a realistic model of many core architecture and we study the hardware cost of our proposal, showing that our approach can lead to a 50% reduction of both external memory accesses and application execution time.

Published in:

VLSI (ISVLSI), 2012 IEEE Computer Society Annual Symposium on

Date of Conference:

19-21 Aug. 2012