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A 2.63 Mbit/s VLSI Implementation of SISO Arithmetic Decoders for High Performance Joint Source Channel Codes

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3 Author(s)
Zezza, S. ; Department of Electronics, Politecnico di Torino, Torino, Italy ; Nooshabadi, S. ; Masera, G.

This paper highlights the implementation challenges faced by the current high performing error resilient joint source channel coding (JSCC) techniques based on the concept of soft-input soft-output (SISO) decoding of arithmetic codes (AC). Further, it proposes several efficient algorithmic and a very large scale integration (VLSI) architectural techniques to improve the throughput performance of SISO for JSCC. The VLSI hardware implementation of the proposed algorithm, when implemented on a 90 nm standard cells technology running at 588 MHz, achieves a decoding throughput of up to 2.63 Mbits/s capable of decoding QCIF format for video conferencing.

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Circuits and Systems I: Regular Papers, IEEE Transactions on  (Volume:60 ,  Issue: 4 )