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A Leakage-Current-Recycling Phase-Locked Loop in 65 nm CMOS Technology

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3 Author(s)
I-Ting Lee ; Graduate Institute of Electronics Engineering and Department of Electrical Engineering, National Taiwan University, Taipei, Taiwan, R. O. C. ; Yun-Ta Tsai ; Shen-Iuan Liu

A leakage-current-recycling technique is presented for phase-locked loops (PLLs) in nanoscale CMOS technology. The leakage current of the PMOS capacitor in a PLL is recycled to supply the power for a voltage-controlled oscillator, a divider, and a dual-mode phase-frequency detector. This PLL is fabricated in a 65 nm CMOS technology. The measured peak-to-peak jitter and rms jitter of this PLL at 640 MHz are 52.2 ps and 9.6 ps, respectively. Its power consumption is 1.2 mW for a 1.2 V supply voltage.

Published in:

IEEE Journal of Solid-State Circuits  (Volume:47 ,  Issue: 11 )