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A flexible, software-configurable wireless receiver is implemented in 65 nm CMOS. The receive chain consists of wideband LNA and mixer, baseband amplifiers, and a 7-bit 21 MS/s filtering SAR ADC. This filtering ADC embeds a highly-integrated and configurable DT FIR/IIR filter to replace dedicated filtering stages. The tap length and coefficients of the embedded FIR filter are configurable from 16 to 64 taps and 0 to 6 units, respectively. Interleaving of the SAR and DT filter sampling processes in the ADC maximizes the conversion rate and facilitates IIR filtering. The prototype receiver supports several standards and bands. In packet tests, the prototype exceeds the sensitivity and jammer resistance requirements of both the 915 MHz and 2450 MHz bands of IEEE 802.15.4 while consuming 4.0 mW and 5.5 mW, respectively. The receiver is also demonstrated with the DSSS specification of IEEE 802.11.