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High performance compressive sensing reconstruction hardware with QRD process

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2 Author(s)
Jerome L. V. M. Stanislaus ; Dept. of Comput. Sci. & Electr. Eng., Univ. of Maryland, Baltimore, MD, USA ; Tinoosh Mohsenin

This paper presents a high performance architecture for the reconstruction of compressive sampled signals using Orthogonal Matching Pursuit (OMP) algorithm. Q-R decomposition (QRD) process is used for the matrix inverse core and a new algorithm for finding fast inverse square root of a fixed point number is also implemented to support the QRD process. The optimized architecture takes 256-length input vector and 64 measurement data, and reconstructs a signal of sparsity 8. The design is implemented in 65 nm CMOS which runs at 165 MHz and occupies 0.69 mm2, total reconstruction takes 13.7 μs. The implementation on Xilinx FPGA Virtex-5 takes 27.12 μs to reconstruct a 256-length signal of sparsity 8. The same architecture for 128-length signal of sparsity 5 on Virtex-5 is 2.4 times faster than the state-of-the-art implementation.

Published in:

2012 IEEE International Symposium on Circuits and Systems

Date of Conference:

20-23 May 2012