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Adaptive hardware by dynamic reconfiguration for the Solar Orbiter PHI instrument

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7 Author(s)
Fiethe, B. ; IDA TU Braunschweig, Braunschweig, Germany ; Bubenhagen, F. ; Lange, T. ; Michalik, H.
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A limited telemetry rate combined with a large amount of scientific information retrieved from the camera systems of the Polarimetric and Helioseismic Imager (PHI) instrument on Solar Orbiter demand that classical ground processing steps like determination of scientific parameters need to be performed already on-board. Field-Programmable Gate Arrays (FPGAs) with large logic density provide a highly flexible platform to implement such sophisticated capabilities. Specifically, radiation tolerant space suitable SRAM-based FPGAs have significantly improved flexibility of high reliable systems for space applications and have already been proven in many space missions. Furthermore, the potential of SRAM-based FPGAs to support dynamic (partial) reconfiguration allows a flexible use of the available hardware (HW) platform in a TimeSpace Partitioning (TSP) manner. For the PHI Data Processing Unit (DPU), the seamless reconfigurability of these FPGAs enables multiple use of the FPGA resources during different modes of operation, i.e. one dedicated configuration for image acquisition and a different configuration for subsequent data processing. Other advantages like enhanced flexibility of a system or in-flight adaptation to changing mission requirements are presented. The basic structure proposed for the PHI DPU design is based on the results of the ESA study for a Dynamically Reconfigurable Processing Module (DRPM). The communication architecture employs our own SpaceWire based System-on-Chip Wire (SoCWire), which is able to connect reconfigurable modules to a host system with the capability to isolate these modules logically and physically. For safe in-flight update data integrity of the uploaded HW code must be guaranteed from ground upload until storage in configuration memory to maintain system qualification. This is taken into account especially in view of possible Single Event Upsets (SEUs) errors in configuration memory. A reasonable separation of the required functio- al modules in different configurations for the FPGAs is shown. The necessary reconfiguration of the FPGAs has no operational impact. Finally, a comparative summary of needed resources clearly outlines the advantages of a dynamically reconfigurable configuration, resulting in mission cost reduction.

Published in:

Adaptive Hardware and Systems (AHS), 2012 NASA/ESA Conference on

Date of Conference:

25-28 June 2012

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