By Topic

A bus-efficient low-latency network interface for the PDSS multicomputer

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
C. S. Steele ; USC Inf. Sci. Inst., Marina del Rey, CA, USA ; J. Draper ; J. Koller ; C. LaCour

The Packaging-Driven Scalable Systems multicomputer (PDSS) project uses several innovative interconnect and routing techniques to construct a low-latency, high-bandwidth (1.3 GB/s) multicomputer network. The PDSS network interface provides a low-latency interface between the network and the processing nodes that allows unprivileged code to initiate network operations while maintaining a high level of protection. The interface design exploits processor-bus cache coherence protocols to deliver very-low-latency cache-to-cache communications between processing nodes. Network operations include a variety of transfers of cache-line-sized packets, including remote read and write, and a distributed barrier-synchronization mechanism. Despite performance-limiting flaws, the initial single-chip implementation of the network router and interface achieves gigabit/s bandwidth and microsecond cache-to-cache latencies between nodes using commodity processor and memory components

Published in:

High Performance Distributed Computing, 1997. Proceedings. The Sixth IEEE International Symposium on

Date of Conference:

5-8 Aug 1997