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Electrical, thermal and mechanical impact of 3D TSV and 3D stacking technology on advanced CMOS devices — Technology directions

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1 Author(s)
Beyne, E. ; IMEC, Leuven, Belgium

3D integration technology using thin die and Through-Silicon-Via, TSV, connections affect transistor and circuit behavior through electrical, mechanical and thermal interactions. The roadmap for further 3D technology development should focus on minimizing these effects.

Published in:

3D Systems Integration Conference (3DIC), 2011 IEEE International

Date of Conference:

Jan. 31 2012-Feb. 2 2012