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A 32GHz delay locked loop with a full rate sub-psec phase detector in 40nm CMOS

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5 Author(s)
Aryanfar, F. ; Rambus Inc., Sunnyvale, CA 94089, USA ; Ho, E. ; Shi, X. ; Desai, K.
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A mm-wave delay locked loop (DLL) using a full rate sub-psec phase detector (PD) is presented. The PD employs a differential lumped hybrid coupler to create and combine quadrature phase components of the input signals and performs amplitude measurement in order to measure phase difference between the input signals. The DLL and PD were implemented using the TSMC 40nm LP CMOS process and measured using on die probing. PD works from 19.75 to 41GHz while requiring significantly less input power than a divider based approach. The DLL has an 800MHz locking range that is centered at 32.3GHz. It consumes 10mA from a 1.1V supply.

Published in:

Microwave Symposium Digest (MTT), 2012 IEEE MTT-S International

Date of Conference:

17-22 June 2012

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