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Garp: a MIPS processor with a reconfigurable coprocessor

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2 Author(s)
Hauser, J.R. ; California Univ., Berkeley, CA, USA ; Wawrzynek, J.

Typical reconfigurable machines exhibit shortcomings that make them less than ideal for general-purpose computing. The Garp Architecture combines reconfigurable hardware with a standard MIPS processor on the same die to retain the better features of both. Novel aspects of the architecture are presented, as well as a prototype software environment and preliminary performance results. Compared to an UltraSPARC, a Garp of similar technology could achieve speedups ranging from a factor of 2 to as high as a factor of 24 for some useful applications

Published in:

Field-Programmable Custom Computing Machines, 1997. Proceedings., The 5th Annual IEEE Symposium on

Date of Conference:

16-18 Apr 1997

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