Referenced Items are not available for this document.
We present the design and implementation of an asynchronous Global Positioning System (GPS) base band processor architecture designed with a combination of Quasi-Delay-Insensitive (QDI) and bundled-data techniques, with a focus on minimizing power consumption. All subsystems run at their natural frequency without clocking and all signal processing is done on-the-fly. Transistor-level simulations show that our system consumes only 1.4mW with position 3-D rms error below 4 meters, comparing favorably to other contemporary GPS base band processors.
Published in:
Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on
Date of Conference: 7-9 May 2012
- Page(s):
- 33 - 40
- ISSN :
- 1522-8681
- Print ISBN:
- 978-1-4673-1360-5
- INSPEC Accession Number:
- 12880399
- Conference Location :
- Lyngby
- Digital Object Identifier :
- 10.1109/ASYNC.2012.20
- Product Type:
- Conference Publications
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