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This paper presents a statistical framework to analyze the performance of CMOS digital circuit in the presence of process variations considering a variety of timing methodologies. We first develop an analytical model that accurately predicts the circuit variability across a wide range of supply voltage and logic depth in 65nm CMOS technology. We then present a statistical analysis model to estimate the respective performance overheads of synchronous, asynchronous bundled-data and dual-rail timing schemes under process variations. The proposed analysis framework combining variability and statistical performance models, enables designers to efficiently evaluate energy and delay performances of CMOS digital circuit, and determine the optimal timing strategy, pipeline depth and supply voltage in the presence of variability.