By Topic

Statistical Analysis and Optimization of Asynchronous Digital Circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Tsung-Te Liu ; Berkeley Wireless Res. Center, Univ. of California, Berkeley, Berkeley, CA, USA ; Jan M. Rabaey

This paper presents a statistical framework to analyze the performance of CMOS digital circuit in the presence of process variations considering a variety of timing methodologies. We first develop an analytical model that accurately predicts the circuit variability across a wide range of supply voltage and logic depth in 65nm CMOS technology. We then present a statistical analysis model to estimate the respective performance overheads of synchronous, asynchronous bundled-data and dual-rail timing schemes under process variations. The proposed analysis framework combining variability and statistical performance models, enables designers to efficiently evaluate energy and delay performances of CMOS digital circuit, and determine the optimal timing strategy, pipeline depth and supply voltage in the presence of variability.

Published in:

Asynchronous Circuits and Systems (ASYNC), 2012 18th IEEE International Symposium on

Date of Conference:

7-9 May 2012