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1Mb 4T-2MTJ nonvolatile STT-RAM for embedded memories using 32b fine-grained power gating technique with 1.0ns/200ps wake-up/power-off times

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9 Author(s)
Ohsawa, T. ; Center for Spintronics Integrated Syst., Tohoku Univ., Sendai, Japan ; Koike, H. ; Miura, S. ; Honjo, H.
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A 1Mb nonvolatile STT-RAM using the 4T-2MTJ cell is designed and fabricated using 90nm CMOS and MTJ processes. 32 cells along a word line (WL) are simultaneously power-gated with quick wake-up/power-off times of 1.0ns/200ps, respectively, to reduce operation power and to eliminate standby power of the chip. The cell is experimentally shown to retain data with static noise margin (SNM) 0.32V under Vdd=1V. The 1Mb chip with 2.19μm2 cell is successfully operated with array access time of 8ns and read power of 10.7mW under 10ns cycle. The macro size of 1Mb STT-RAM is predicted to become smaller than the 1Mb 6T-SRAM in 45nm and beyond.

Published in:

VLSI Circuits (VLSIC), 2012 Symposium on

Date of Conference:

13-15 June 2012

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