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A 34% PAE, 18.6dBm 42–45GHz stacked power amplifier in 45nm SOI CMOS

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6 Author(s)
Agah, A. ; Dept. of Electr. & Comput. Eng., Univ. of California, San Diego, La Jolla, CA, USA ; Dabag, H. ; Hanafi, B. ; Asbeck, P.
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A two-stack 42-45GHz power amplifier is implemented in 45nm SOI CMOS. Transistor stacking allows increased drain biasing to increase output power. Additionally, shunt inter-stage matching is used and improves PAE by more than 6%. This amplifier exhibits 18.6dBm saturated output power, with peak power gain of 9.5dB. It occupies 0.3mm2 including pads while achieving a peak PAE of 34%. The PAE remains above 30% from 42 to 45GHz.

Published in:

Radio Frequency Integrated Circuits Symposium (RFIC), 2012 IEEE

Date of Conference:

17-19 June 2012

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