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A 6-Gbit/s Hybrid Voltage-Mode Transmitter With Current-Mode Equalization in 90-nm CMOS

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2 Author(s)
Young-Hoon Song ; Department of Electrical and Computer Engineering, Texas A&M University, College Station, TX, USA ; Samuel Palermo

Low-power (LP) high-speed serial I/O transmitters which include equalization to compensate for channel frequency-dependent loss are required to meet the aggressive link energy-efficiency targets of future systems. This brief presents an LP serial-link-transmitter design that utilizes an output stage which combines a voltage-mode driver, which offers low static-power dissipation, and current-mode equalization, which offers low complexity and dynamic-power dissipation. The utilization of current-mode equalization decouples the equalization settings and termination impedance, allowing for a significant reduction in predriver complexity relative to segmented voltage-mode drivers. Proper transmitter series termination is set with an impedance control loop which adjusts the on-resistance of the output transistors in the driver voltage-mode portion. Further reductions in dynamic-power dissipation are achieved through scaling the serializer and local clock distribution supply with data rate. Fabricated in a 1.2-V 90-nm LP CMOS process, the transmitter supports an output swing range of 100–400 \hbox {mV}_{{\rm ppd}} and up to 6 dB of equalization and includes output-duty-cycle control. The transmitter achieves 6-Gbit/s operation at 1.26-pJ/bit energy efficiency with 300- \hbox {mV}_{{\rm ppd}} output swing and 3.72-dB equalization.

Published in:

IEEE Transactions on Circuits and Systems II: Express Briefs  (Volume:59 ,  Issue: 8 )