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The functional delay-fault models, which are based on the input stimuli and correspondent responses at the outputs, cover transition faults at the gate level quite well. This statement forms the basis for the analysis and comparison of different methods of design for testability (DFT) using software prototype model of the circuit and to select the most appropriate one before the structural synthesis of the circuit. Along with known DFT methods (enhanced scan, launch-on-shift scan and launch-on-capture scan), the authors introduce the method, which is based on the addition of new connections to the circuit in the non-scan testing mode. In order to assess the DFT methods, the functional test is generated for the analysed circuit and the functional delay-fault coverage for this test is evaluated. Each of the considered DFT methods has its own advantages and disadvantages, since they have different delay fault coverage, and require different hardware for their implementation. These differences depend on the function of circuit. The experimental results are provided for the ITC'99 benchmark circuits. The obtained results proved the applicability of the proposed method.