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Testing of Stuck-Open Faults in Nanometer Technologies

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6 Author(s)
Champac, V. ; Dept. of Electron. Eng., Inst. Nac. de Astrofis., Opt. y Electron. (INAOE), Puebla, Mexico ; Hernandez, J.V. ; Barcelo, S. ; Gomez, R.
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Failure analysis and fault modeling of integrated circuits have always been fields that require continuous revision and update as manufacturing processes evolve. This paper discusses the new face of the well-known transistor stuck-open fault model in modern nanometer technologies and proposes new detection methods that improve the robustness of tests.

Published in:

Design & Test of Computers, IEEE  (Volume:29 ,  Issue: 4 )

Date of Publication:

Aug. 2012

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