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A prototype 10-bit 80-MS/s pipelined analog-to-digital converter (ADC) implemented in a 0.25-μm CMOS process is described. The prototype uses a combination of time-interleaved and lookahead operations to allow one clock period for comparator regeneration, reducing the bit error rate (BER) due to comparator metastability by a factor between 104 and 106. Also, the front-end sample-and-hold amplifier (SHA) previously used to provide a 1/2 clock period of regeneration time for the first-stage comparators in a lookahead pipelined ADC is eliminated , , reducing the power consumption and the input-referred noise. The analog power dissipation is 72 mW from a 2.5-V supply. At a sampling rate of 80 MS/s, the prototype achieves a peak signal-to-noise-and-distortion ratio of 58.3 dB for an input frequency of 80 kHz. Also, for a comparator bias current of 100 μA, extrapolations from measurements show that the BER is <;10-15 errors/sample.
Date of Publication: Sept. 2012