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A new multi-level differential-time-signaling (DTS) architecture for serial communication links is presented in this paper. The proposed system concentrates the transmitted signal energy in a smaller bandwidth than conventional architectures, allowing higher data rates for a given channel, and uses simple circuitry compared to other serial links, resulting in less power consumption and chip area. A 6-bit 3Gb/s three-level DTS link has been simulated using Cadence tools in a mixed-signal 90nm CMOS process. The eye diagrams of the transmitted signal and of the received signal at the end of a 40-inch FR-4 channel are presented. The spectral energy content in the transmitted signal is compared to our two-level DTS architecture and to the standard Serializer/Deserializer (SerDes) architecture to illustrate the advantages.
Date of Conference: 14-16 May 2012