Referenced Items are not available for this document.
3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images.
Published in:
Semiconductor Manufacturing, IEEE Transactions on
(Volume:25
,
Issue:
3
)
Date of Publication: Aug. 2012
- Page(s):
- 355 - 364
- ISSN :
- 0894-6507
- INSPEC Accession Number:
- 12894902
- Digital Object Identifier :
- 10.1109/TSM.2012.2202798
- Product Type:
- Journals & Magazines
- Date of Publication :
- 05 June 2012
- Date of Current Version :
- 31 July 2012
- Issue Date :
- Aug. 2012
- Sponsored by :
- IEEE Components, Packaging and Manufacturing Technology Society
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