Scheduled System Maintenance:
On Monday, April 27th, IEEE Xplore will undergo scheduled maintenance from 1:00 PM - 3:00 PM ET (17:00 - 19:00 UTC). No interruption in service is anticipated.
By Topic

Test Structures for Characterization of Through-Silicon Vias

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

5 Author(s)
Stucchi, M. ; Interuniv. Micro Electron. Center, Leuven, Belgium ; Perry, D. ; Katti, G. ; Dehaene, W.
more authors

3-D chip stacking using through-silicon vias (TSVs) requires accurate characterization of the TSV, the thinned silicon, and the stacked dies. This paper proposes a set of test structures specifically designed to address the electrical characterization of TSV in terms of resistance, capacitance, leakage, yield, and their impact on the 2-D interconnects of the stacked dies. Examples of the use of these structures are presented, and the observed electrical behaviors are explained with the support of FIB cross-section images.

Published in:

Semiconductor Manufacturing, IEEE Transactions on  (Volume:25 ,  Issue: 3 )