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Rapid single-flux quantum circuits are generally biased in parallel with a common ground. As the integration scale increases, the total dc bias current can become too large to be practical. Applications such as large-scale Josephson-junction circuits for petaflops computers must avoid prohibitive dc bias requirements. Serial dc bias of multiple-circuit modules enables more efficient and effective operation of large circuits. This paper describes a circuit containing 1488 junctions in which the bias current was reused 16 times to reduce the required bias from ~100 mA to roughly 12 times less. We report initial results in which this circuit was operated up to 50 Gb/s with a negligible error rate.