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An evaluation of CMOS adders in deep submicron processes

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2 Author(s)
Gera, R.J. ; Dept. of Electr. Eng., Univ. of Texas at Tyler, Tyler, TX, USA ; Hoe, D.H.K.

An evaluation of various adders that are representative of different CMOS logic design styles is carried out for nanoscale CMOS technologies using a Predictive Technology Model from [1]. The adders under consideration are the static CMOS mirror adder, the Complementary Pass-transistor Logic (CPL) adder, the Transmission Gate Adder (TGA), and the Hybrid-CMOS adder (HCMOS). The adders are evaluated in terms of delay, power dissipation, voltage scalability, and area. Because scaling of the voltage supply to less than 1 V results in gate overdrive factors of less than 0.5 V, it is found that adders that maintain the optimum signal paths for both high and low signals (the mirror and TGA adders) had the best performance metrics when scaled to the deep submicron regime. The adders that rely upon PMOS feedback for signal restoration (the CPL and HCMOS designs) experienced significant degradation in performance at low power supply voltages.

Published in:

System Theory (SSST), 2012 44th Southeastern Symposium on

Date of Conference:

11-13 March 2012