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A high-speed parallel sensing scheme for multi-level non-volatile memories

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4 Author(s)
C. Calligaro ; Dipt. di Elettronica, Pavia Univ., Italy ; R. Gastaldi ; A. Manstretta ; G. Torelli

A parallel sensing scheme for multi-level non-volatile memories (ML NVM) is presented. A single comparison step is used to achieve high sensing speed. To this purpose, a high-speed low-voltage current comparator is used. Experimental evaluations on a 0.6-μm EPROM test chip demonstrated the feasibility of 4-level-cell NV MLMs from the sensing standpoint. A read throughput of 12 MB/s is achieved with the proposed 4-level-cell memory architecture. Multi-level storage is achieved by using a program-verified scheme to obtain tight cell threshold voltage distribution. Overall sensing area overhead for a 32-Mbit chip is in the range of 1%

Published in:

Memory Technology, Design and Testing, 1997. Proceedings., International Workshop on

Date of Conference:

11-12 Aug 1997